The present disclosure relates to high speed memories used in systems in which a communications channel exists between the memory and a control device and, more particularly, to methods and apparatus for characterizing the communications channel.
In a typical computer system, a processor interfaces with a memory device over a bus, typically through a memory controller. When a controller submits a read request to a memory device, the response from the memory device can be read by the controller from the bus after a delay of time, referred to as a “read latency.” If a controller submits a write request, a memory device in the memory system can then receive the data from the bus and start to capture the data for storage after a certain “write latency.”
The amount of latency can vary depending on the type of device and the communications channel. The amount of latency can also vary depending upon the type of request. For example, a memory subsystem may require 10-15 nanoseconds to respond to a read request, but only 5-10 nanoseconds to respond to a write request.
A memory controller, in advance of issuing a memory request, typically stores a specified latency value for each type of request and for each type of device. Therefore, when issuing a request, the controller can determine the period of time that it must wait before providing data to or receiving data from the bus. That period of time may be dependent, in part, on the characteristics of the communications channel.
There have been several proposals for initialization patterns for characterizing high-speed DRAM communications channels. One such proposal was given for SLDRAM in which a pseudo-random pattern was transmitted over the communications channel in the DRAM subsystem. A pseudo-random pattern was chosen because it has a detectable repetitive pattern while, at the same time, it provides a high degree of random signal transitions to adequately exercise the communications channel in a DRAM subsystem. Internal circuits of the DRAM and the controller are adjusted based on the successful detection of the pseudo-random pattern to compensate for channel and process imperfections in the memory subsystem.
One disadvantage with transmitting a pseudo-random pattern is the relative complexity of detecting the pseudo-random pattern compared to a more simplified pattern, such as a repeating pattern of 101010. Thus, a need exists for a method and apparatus of adequately exercising a communications channel with signals having a high degree of random signal transitions while at the same time simplifying the task of analyzing the received signal.